XC2C64A-7VQG44I

CPLD, QFP, –0.5 to 2.0 V, Advanced design security, Optional bus-hold, PLA architecture, Flexible clocking modes

Rated 5 Rating 5 | reviews | Write a review

Price:: US $1.50~2.50 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $1.50~2.50

PartNumber:: XC2C64A-7VQG44I

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Mr. Jack's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-09-26

From Other Seller

Part Number:XC2C64A-7VQG44I
US $1.50 - 2.50
ECA1HHG4R7

US $10.00 - 10.00 / Piece
(0) Remove
ECA1HHG220

US $2.00 - 10.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The XC2C64A-7VQG44I is a CPLD. The XC2C64A-7VQG44I delivers the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3 family in a single CPLD. This means that the exact same parts of the XC2C64A-7VQG44I can be used for high-speed data communications/computing systems and leading edge portable products, with the added benefit of In System Programming. Low power consumption and high-speed operation are combined into the XC2C64A-7VQG44I that is easy to use and cost effective.

Parametrics

XC2C64A-7VQG44I absolute maximum ratings: (1)VCC, Supply voltage relative to GND: –0.5 to 2.0 V; (2)VI, Input voltage relative to GND: –0.5 to 4.0 V; (3)TA, Ambient Temperature (C-grade): 0 to 70℃; Ambient Temperature (I-grade): –40 to 85℃; (4)TJ, Maximum junction temperature: –40 to 150℃; (5)TSTR, Storage temperature: –65 to 150℃.

Features

XC2C64A-7VQG44I features: (1)Optimized for 1.8V systems: Industry fastest low power CPLD; Densities from 32 to 512 macrocells; (2)Industry best 0.18 micron CMOS CPLD: Optimized architecture for effective logic synthesis ; Multi-voltage I/O operation — 1.5V to 3.3V ; (3)Fastest in system programming; (4)1.8V ISP using IEEE 1532 (JTAG) interface; (5)On-The-Fly Reconfiguration (OTF); (6)IEEE1149.1 JTAG Boundary Scan Test; (7)Optional Schmitt trigger input (per pin); (8)Multiple I/O banks on all devices; (9)Unsurpassed low power management; (10)DataGATE external signal control: Flexible clocking modes; (11)Optional DualEDGE triggered registers; (12)Clock divider (÷ 2,4,6,8,10,12,14,16); (13)CoolCLOCK ; (14)Global signal options with macrocell control; (15)Multiple global clocks with phase selection per macrocell.