Product Summary
The 74AHC573 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard No. 7A. The 74AHC573 is an octal D-type transparent latche featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches.
Parametrics
74AHC573 absolute maximum ratings: (1)VCC DC supply voltage: -0.5 to +7.0 V; (2)VI input voltage range: -0.5 to +7.0 V; (3)IIK DC input diode current: -20 mA; (4)IOK DC output diode current: ±20 mA; (5)IO DC output source or sink current:±25 mA; (6)ICC DC VCC or GND current:±75 mA; (7)Tstg storage temperature range: -65 to +150℃; (8)PD power dissipation per package: 500 mW.
Features
74AHC573 features: (1)ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-Aexceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V; (2)Balanced propagation delays; (3)All inputs have Schmitt-trigger actions; (4)Common 3-state output enable input; (5)Functionally identical to the 56’ and 373; (6)Inputs accepts voltages higher than VCC; (7)For AHC only: operates with CMOS input levels; (8)For AHCT only: operates with TTL input levels; (9)Specified from -40 to +85 and +125℃.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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74AHC573 |
Other |
Data Sheet |
Negotiable |
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74AHC573BQ,115 |
NXP Semiconductors |
Latches D-TYPE 8CIRC 7V |
Data Sheet |
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74AHC573D |
NXP Semiconductors |
Latches OCTAL LATCH XVR W/DUAL ENABLE |
Data Sheet |
Negotiable |
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74AHC573D,112 |
NXP Semiconductors |
Latches OCTAL LATCH XVR |
Data Sheet |
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74AHC573D,118 |
NXP Semiconductors |
Latches OCTAL LATCH XVR |
Data Sheet |
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74AHC573D-T |
NXP Semiconductors |
Latches OCTAL LATCH XVR W/DUAL ENABLE |
Data Sheet |
Negotiable |
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74AHC573PW |
NXP Semiconductors |
Latches OCTAL LATCH XVR W/DUAL ENABLE |
Data Sheet |
Negotiable |
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74AHC573PW,118 |
NXP Semiconductors |
Latches OCTAL LATCH XVR |
Data Sheet |
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