MC68HC711E9CFNE3

Product Summary

The MC68HC711E9CFNE3 is an 8-bit microcontroller unit (MCU). The MC68HC711E9CFN3 combines the M68HC11 central processor unit (CPU) with high-performance, on-chip peripherals. The MC68HC711E9CFNE3 is comprised of many devices with various configurations of Random-access memory (RAM), Read-only memory (ROM), Erasable programmable read-only memory (EPROM), Electrically erasable programmable read-only memory (EEPROM), Several low-voltage devices are also available.

Parametrics

MC68HC711E9CFNE3 absolute maximum ratings: (1)Supply voltage VDD:–0.3V to +7.0 V; (2)Input voltage VIn:–0.3 to +7.0 V; (3)Current drain per pin(1) excluding VDD, VSS, AVDD, VRH, VRL, and XIRQ/VPPE ID: 25mA; (4)Storage temperature TSTG:–55℃ to +150℃.

Features

MC68HC711E9CFNE3 features: (1)M68HC11 CPU; (2)Power-saving stop and wait modes; (3)Low-voltage devices available (3.0V to 5.5V); (4)0, 256, 512, or 768 bytes of on-chip RAM, data retained during standby; (5)0, 12, or 20 Kbytes of on-chip ROM or EPROM; (6)0, 512, or 2048 bytes of on-chip EEPROM with block protect for security; (7)2048 bytes of EEPROM with selectable base address in the MC68HC811E2; (8)Asynchronous non-return-to-zero (NRZ) serial communications interface (SCI); (9)Additional baud rates available on MC68HC(7)11E20; (10)Synchronous serial peripheral interface (SPI); (11)8-channel, 8-bit analog-to-digital (A/D) converter; (12)Three input capture (IC) channels; (13)Four output compare (OC) channels; (14)One additional channel, selectable as fourth IC or fifth OC; (15)8-bit pulse accumulator; (16)Real-time interrupt circuit; (17)Computer operating properly (COP) watchdog system; (18)38 general-purpose input/output (I/O) pins; (19)52-pin plastic-leaded chip carrier (PLCC); (20)52-pin windowed ceramic leaded chip carrier (CLCC); (21)52-pin plastic thin quad flat pack, 10 mm x 10 mm (TQFP); (22)64-pin quad flat pack (QFP); (23)48-pin plastic dual in-line package (DIP), MC68HC811E2 only; (24)56-pin plastic shrink dual in-line package, .070-inch lead spacing (SDIP).

Diagrams