(China (Mainland))
Product Summary
The EPM3064ALC44-4 is a Programmable Logic Device. It is based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EPM3064ALC44-4 operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM3064ALC44-4 in the –4, –5, –6, –7, and –10 speed grades is compatible with the timing requirements of the PCI Special Interest Group (PCI SIG).
Parametrics
EPM3064ALC44-4 absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –0.5 to 4.6 V; (2)VI, DC input voltage: –2.0 to 5.75 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG Storage temperature No bias : –65 to 150 ℃; (5)TA, Ambient temperature Under bias: –65 to 135 ℃; (6)TJ, Junction temperature PQFP and TQFP packages, under bias: 135 ℃.
Features
EPM3064ALC44-4 features: (1)High performance, low cost CMOS EEPROM based programmable logic devices (PLDs) built on a MAXR architecture; (2)3.3-V in-system programmability (ISP) through the built in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability; (3)Built in boundary-scan test (BST) circuitry compliant with IEEE Std 1149.1-1990; (4)High–density PLDs ranging from 600 to 10,000 usable gates; (5)4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz; (6)MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels; (7)Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGA packages.
Diagrams
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 EPM3064ALC44-4 |
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IC MAX 3000A CPLD 64 44-PLCC |
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EPM3064ALC44-4N |
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IC MAX 3000A CPLD 64 44-PLCC |
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